1. Field of the Invention
The invention relates to timer generation corresponding to timer request from a plurality of task processes such as an application program executed by a computer and, particularly, relates to a timer apparatus, a timer processing method, and an electronic apparatus that use a variable timer circuit.
2. Description of the Related Art
While various electronic apparatuses such as portable terminal apparatuses are provided with CPUs (Central Processing Units) in control systems to achieve timer generation and perform control to generate a plurality of necessary time periods with software with the use of periodical interruptions (hereinafter, “basic timing”) at regular intervals, for example, 10 [msec] or 5 [msec], currents are increased by operating the CPUs periodically.
Such timer generation is included in Japanese Patent Application Laid-Open Publication Nos. 2000-259429, 1987-274815, and 1995-28554; Japanese Patent Application Laid-Open Publication No. 2000-259429 discloses managing timer events in a plurality of systems in an integrated fashion to achieve a plurality of different system operations with one timer apparatus; Japanese Patent Application Laid-Open Publication No. 1987-274815 discloses a timer apparatus that stores, updates, or detects time-out of timer values corresponding to a plurality of control apparatus to enable the clocked timer values or the time-out to be taken out to the outside for managing the timing of the control apparatuses or the time period until time-out; and Japanese Patent Application Laid-Open Publication No. 1995-28554 discloses a timer count mode that determines counting priorities from in ascending order of timer values and that counts the timer value with a timer start request to issue a time-up notification concurrently with the completion of the counting.
By the way, as in the case of Japanese Patent Application Laid-Open Publication No. 1995-28554, in an updating method of a timer value, high-speed interruption response performance is required for receiving timing interruptions of timer updates and, to perform control in short time intervals, a high-speed CPU is required to shorten the timer update timing from 10 [msec] to 2 [msec], for example. Such a high-speed CPU causes increase in consumption currents. If the operating clock of the CPU is cut down to reduce the consumption currents, omission in the timer processes, etc. may be caused.
Japanese Patent Application Laid-Open Publication Nos. 2000-259429, 1987-274815, and 1995-28554 do not disclose or indicate such problems and do not describe or indicate means for solving the problems.